The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and specifically to a method of laying out conductive patterns employed in a semiconductor integrated circuit device using a multilayer interconnection.
A semiconductor integrated circuit device comprises circuits made up of macro cells, which are utilized in combination. The disposition or arrangement of the macro cells and the layout of conductive patterns lying between the macro cells are determined by a computer system such as CAD, based on layout data. Upon the determination of such a layout, priority is placed on the shortening of the length of each conductive pattern, and a decision as to which layer in a multilayer interconnection should be used, is given a low priority. Incidentally, such a layout method and an automatic layout device have been disclosed in Japanese Patent Application Laid-Open No. Hei 10(1998)-125795.
As described above, top-layer conductive patterns of the multilayer interconnection are often used for connection to electrode pads, and there is a low possibility that the conductive patterns between the macro cells, for example, will be used. Therefore, when it is desired to perform an electrical analysis on internal operating waveforms or the like of a completed semiconductor integrated circuit device, a wiring layer must be peeled and tested, so that it becomes extremely difficult. In the invention disclosed in Japanese Patent Application No. 2000-243847, an empty space unformed with conductive patterns employed in a semiconductor integrated circuit device is utilized to electrically 10 make a connection from a point to be measured at a lower layer of a multilayer interconnection to an observed pad on the uppermost or top-layer conductive pattern through the lower layer to its upper layer with a view toward solving such a problem. Thus, the electrical analysis is allowed from the observed pad.
However, such a method has a possibility that since the empty space is necessary for the conductive patterns employed in the semiconductor integrated circuit device, the semiconductor integrated circuit device will increase in size. There is a need to execute work which takes time and trouble that since the observed pad and an intermediate wiring layer or the like used for its electrical connection are additionally provided after the completion of the layout and wiring employed in the semiconductor integrated circuit device, a parasitic capacitance between adjacent conductive patterns, etc. must be re-calculated.
The present invention may provide a method of laying out conductive patterns employed in a semiconductor integrated circuit device, which is capable of performing an electrical analysis on internal operating waveforms or the like without peeling a wiring layer.
A method of forming conductive patterns comprises preparing layout data about macro cells, preparing data about layouts of top-layer conductive pattern metal cells and preparing data about conductive patterns between the macro cells, inputting to the macro cells and outputting from the macro cells. Then measurement-required points of the conductive patterns lying between the macro cells are specified. The top-layer conductive pattern metal cell is interposed in each of the measurement-required points. Finally, layouts of the macro cells and conductive patterns are determined so that layout data is created.